View M58LV064A150ZA1T_4898639.PDF datasheet online --- IC-ON-LINE

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1/65 preliminary data december 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m58lv064a m58lv064b 64 mbit (4mb x16 or 2mb x32, uniform block, burst) 3v supply flash memories features summary wide data bus for high bandwidth C m58lv064a: x16 C m58lv064b: x16/x32 supply voltage Cv dd = 3.0 to 3.6v m58lv064 core supply Cv ddq = 1.8 to v dd for i/o buffers synchronous/asynchronous read C synchronous burst read C pipelined synchronous burst read C asynchronous random read C asynchronous address latch controlled read C page read access time C synchronous burst read up to 66mhz C asynchronous page mode read 150/25ns C random read 150ns programming time C 16 word or 8 double-word write buffer C12 s word effective programming time 64 uniform 64 kword memory blocks block protection/ unprotection program and erase suspend otp security area common flash interface 100,000 program/erase cycles per block electronic signature C manufacturer code: 0020h C device code m58lv064a: 0015h C device code m58lv064b: 0014h figure 1. packages tsop56 (n) 14 x 20mm tbga64 (za) 10 x 13mm tbga80 (za) 10 x13mm tbga tbga
m58lv064a, m58lv064b 2/65 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tsop56 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. tbga64 connections for m58lv064a (top view through package) . . . . . . . . . . . . . . . . 9 figure 5. tbga80 connections for m58lv064b (top view through package) . . . . . . . . . . . . . . . 10 figure 6. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 address inputs (a1-a22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 data inputs/outputs (dq0-dq31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 latch enable (l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 burst address advance (b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 valid data ready (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 word organization (word). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ready/busy (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program/erase enable (v pp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 input/output supply voltage (v ddq ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ground (v ssq ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 automatic low power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2. asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 synchronous burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 synchronous pipelined burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/65 m58lv064a, m58lv064b table 3. synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. address latch cycle for optimum pipelined synchronous burst read . . . . . . . . . . . . . 18 figure 7. synchronous burst read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. example synchronous pipelined burst read operation . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. example burst address advance and burst abort operations . . . . . . . . . . . . . . . . . . . . 20 burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read select bit (m15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 x-latency bits (m14-m11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 y-latency bit (m9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 valid data ready bit (m8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 burst type bit (m7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 valid clock edge bit (m6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 latch enable bit (m3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 burst length bit (m2-m0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. burst type definition (x16 bus width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. burst type definition (x32 bus width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. burst performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 read query command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 write to buffer and program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 set burst configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 block protect command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 blocks unprotect command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . 29 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 vpp status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 block protection status (bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 reserved (bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
m58lv064a, m58lv064b 4/65 table 12. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. ac measurement input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. asynchronous bus read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. asynchronous bus read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. asynchronous latch controlled bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . 37 table 18. asynchronous latch controlled bus read ac characteristics . . . . . . . . . . . . . . . . . . . 37 figure 14. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15. asynchronous write ac waveform, write enable controlled . . . . . . . . . . . . . . . . . . . 39 figure 16. asynchronous latch controlled write ac waveform, write enable controlled. . . . . . 39 table 20. asynchronous write and latch controlled write ac characteristics, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. asynchronous write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . 41 figure 18. asynchronous latch controlled write ac waveforms, chip enable controlled . . . . . 41 table 21. asynchronous write and latch controlled write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 19. synchronous burst read ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. synchronous burst read - continuous - valid data ready output . . . . . . . . . . . . . . . 44 table 22. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21. reset, power-down and power-up ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . 47 table 24. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data 47 figure 23. tbga64 - 10x13mm, 8 x 8 ball array 1mm pitch, package outline . . . . . . . . . . . . . . . 48 table 25. tbga64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, package mechanical data. . . . . . . 48 figure 24. tbga80 - 10x13mm, 8 x 10 ball array, 1mm pitch, package outline . . . . . . . . . . . . . 49 table 26. tbga80 - 10x13mm, 8 x 10 ball array, 1mm pitch, package mechanical data . . . . . . 49 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 27. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 appendix a. block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 28. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 appendix b. common flash interface - cfi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5/65 m58lv064a, m58lv064b table 29. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 33. block status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 34. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 appendix c. flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 25. write to buffer and program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 57 figure 26. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 58 figure 27. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 28. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 60 figure 29. command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . 61 figure 30. command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . 62 figure 31. command interface and program erase controller flowchart (c) . . . . . . . . . . . . . . . . 63 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 35. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
m58lv064a, m58lv064b 6/65 summary description m58lv064 is a 64mbit (4mb x16 or 2mb x32) non- volatile memory that can be read, erased and re- programmed. these operations can be performed using a single low voltage (2.7v to 3.6v) core sup- ply. on power-up the memory default to read mode with an asynchronous bus where it can be read in the same way as a non-burst flash mem- ory. the memory is divided into 64 blocks of 1mbit that can be erased independently so it is possible to preserve valid data while old data is erased. pro- gram and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. the write buffer allows the microprocessor to pro- gram from 4 to 16 words (or from 2 to 8 double words) in parallel, both speeding up the program- ming and freeing up the microprocessor to perform other work. the minimum buffer size for a program operation is a 4 word (or 2 double word) page. a page can only be programmed once between erase operations. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. individual block protection against program or erase is provided for data security. all blocks are protected during power-up. the protection of the blocks is non-volatile; after power-up the protec- tion status of each block is restored to the state when power was last removed. software com- mands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. all program or erase opera- tions are blocked when the program erase enable input vpp is low. the reset/power-down pin is used to apply a hardware reset to the memory and to set the de- vice in deep power-down mode. it can also be used to temporarily disable the protection mecha- nism. in asynchronous mode chip enable, output en- able and write enable signals control the bus op- eration of the memory. an address latch input can be used to latch addresses in latch controlled mode. together they allow simple, yet powerful, connection to most microprocessors, often without additional logic. in synchronous mode all bus read operations are synchronous with the clock. chip enable and out- put enable select the bus read operation; the ad- dress is latched using the latch enable inputs and the address is advanced using burst address advance. the signals are compatible with most microprocessor burst interfaces. a one time programmable (otp) area is included for security purposes. either 1k words (x16 bus width) or 1k double-words (x32 bus width) is available in the otp area. the process of reading from and writing to the otp area is not published for security purposes; contact stmicroelectronics for details on how to use the otp area. the memory is offered in various packages. the m58lv064a is available in tsop56 (14 x 20 mm) and tbga64 (1mm pitch). the m58lv064b is available in tbga80 (1mm pitch).
7/65 m58lv064a, m58lv064b figure 2. logic diagram note: 1. m58lv064b only. table 1. signal names ai03223b 22 a1-a22 w dq0-dq15 v dd m58lv064a m58lv064b e v ss 16 g rp l v ddq b k rb r v pp word (1) dq16-dq31 (1) 16 v ssq a1 address input (x16 bus width only) a2-a22 address inputs dq0-dq15 data inputs/outputs dq16-dq31 data inputs/outputs (x32 bus width of m58lv064b only) b burst address advance e chip enable g output enable k clock l latch enable r valid data ready rb ready/busy rp reset/power-down v pp program/erase enable w write enable word word organization (m58lv064b only) v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground nc not connected internally
m58lv064a, m58lv064b 8/65 figure 3. tsop56 connections dq3 dq9 dq2 dq0 dq6 a16 a17 a18 dq14 dq12 dq10 rb v ddq dq4 dq7 ai03224b m58lv064a 14 1 15 28 29 42 43 56 dq8 v dd dq1 dq11 b a20 a21 nc a19 w a22 r e l k a6 a3 a8 a9 a10 a2 a7 v pp a1 a4 a5 a12 a13 a11 a15 a14 rp v ss nc dq13 dq15 v dd dq5 g v ssq v ss
9/65 m58lv064a, m58lv064b figure 4. tbga64 connections for m58lv064a (top view through package) ai03536 dq6 a1 v ss v dd dq10 v dd dq7 dq5 v ddq dq2 b h dq14 v ssq dq13 d a16 a20 e a9 c a17 a21 a11 a15 k a8 b r a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a7 a3 a4 a5 g f e dq0 l a6 v pp a22 a18 a10 a12 rp dq15 rb dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss nc nc nc nc nc nc nc nc nc nc
m58lv064a, m58lv064b 10/65 figure 5. tbga80 connections for m58lv064b (top view through package) ai03983 v ssq a1 v ss v dd dq27 v dd v ddq dq4 v ss v dd dq1 k v ssq v ddq v ddq d nc a20 a12 a9 c nc a21 a11 a15 dq24 v ss b r a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a6 a3 a4 a5 j e dq18 dq8 a8 a22 a18 a10 v pp rp dq22 dq31 dq19 dq16 dq25 dq6 word dq23 dq13 dq10 dq7 a7 l dq17 dq26 dq30 dq5 dq3 k dq15 dq2 dq12 b dq11 g rb a16 a17 dq28 dq20 dq29 w dq21 dq0 dq9 dq14 f h g e nc nc
11/65 m58lv064a, m58lv064b figure 6. block addresses note: also see appendix a, table 28 for a full listing of the block addresses ai03228b 1 mbit or 64 kwords 3fffffh 3f0000h 1 mbit or 64 kwords 01ffffh 010000h 1 mbit or 64 kwords 00ffffh 000000h 1 mbit or 32 kdouble-words 1fffffh 1f8000h 1 mbit or 32 kdouble-words 00ffffh 008000h 1 mbit or 32 kdouble-words 007fffh 000000h m58lv064a, m58lv064b word (x16) bus width address lines a1-a22 m58lv064b double-word (x32) bus width address lines a2-a22 (a1 is don't care) 1 mbit or 64 kwords 3effffh 3e0000h total of 64 1 mbit blocks 1 mbit or 32 kdouble-words 1f7fffh 1f0000h
m58lv064a, m58lv064b 12/65 signal descriptions see figure 2, logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a1-a22). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the internal state machine. chip enable must be low when selecting the ad- dresses. the address inputs are latched on the rising edge of chip enable, write enable or latch enable, whichever occurs first in a write operation. the address latch is transparent when latch enable is low, v il . the address is internally latched in an erase or program operation. with a x32 bus width, word = v ih , address in- put a1 is ignored; the least significant word is output on dq0-dq15 and the most significant word is output on dq16-dq31. with a x16 bus width, word = v il , the least significant word is output on dq0-dq15 when a1 is low, v il, and the most significant word is output on dq0-dq15 when a1 is high, v ih . data inputs/outputs (dq0-dq31). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the internal state machine. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , the data bus outputs data from the mem- ory array, the electronic signature, the block pro- tection status, the cfi information or the contents of the status register. the data bus is high imped- ance when the chip is deselected, output enable is high, v ih, or the reset/power-down signal is low, v il . when the program/erase controller is active the ready/busy status is given on dq7 while dq0-dq6 and dq8-dq31 are high imped- ance. with a x16 bus width, word = v il , dq16-dq31 are not used and are high impedance. chip enable (e ). the chip enable, e , input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level, i dd1 . output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation. when output enable, g , is at v ih the outputs are high impedance. output enable, g , can be used to inhibit the data output during a burst read operation. write enable (w ). the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able (also see latch enable, l ). reset/power-down (rp ). the reset/power- down pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. a hardware reset is achieved by holding reset/ power-down low, v il , for at least t plph . when reset/power-down is low, v il , the status regis- ter information is cleared and the power consump- tion is reduced to deep power-down level. the device is deselected and outputs are high imped- ance. if reset/power-down goes low, v il ,during a block erase, a write to buffer and program or a block protect/unprotect the operation is aborted and the data may be corrupted. in this case the ready/busy pin stays low, v il , for a maximum tim- ing of t plph + t phrh, until the completion of the re- set/power-down pulse. after reset/power-down goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. note that ready/busy does not fall during a reset, see ready/busy output section. during power-up reset/power-down must be held low, v il. furthermore it must stay low for t vdhph after the supply voltage inputs become stable. the device will then be configured in asynchro- nous random read mode. see table 23 and figure 21, reset, power-down and power-up characteristics, for more details. holding rp at v hh will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. in an application, it is recommended to associate reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset opera- tion occurs while the memory is performing an erase or program operation, the memory may out- put the status register information instead of be- ing initialized to the default asynchronous random read. latch enable (l ). the bus interface can be con- figured to latch the address inputs on the rising edge of latch enable, l . in synchronous bus oper- ations the address is latched on the active edge of the clock when latch enable is low, v il . once latched, the addresses may change without affect- ing the address used by the memory. when latch enable is low, v il , the latch is transparent.
13/65 m58lv064a, m58lv064b clock (k). the clock, k, is used to synchronize the memory with the external bus during synchro- nous bus read operations. the clock can be con- figured to have an active rising or falling edge. bus signals are latched on the active edge of the clock during synchronous bus operations. in synchro- nous burst read mode the address is latched on the first active clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. burst address advance (b ). the burst address advance, b , controls the advancing of the address by the internal address counter during synchro- nous bus operations. burst address advance, b , is only sampled on the active clock edge of the clock when the x- or y- latency time has expired. if burst address ad- vance is low, v il , the internal address counter ad- vances. if burst address advance is high, v ih , the internal address counter does not change; the same data remains on the data inputs/outputs and burst address advance is not sampled until the y-latency expires. the burst address advance, b , may be tied to v il . valid data ready (r). the valid data ready output, r, is an open drain output that can be used to identify if the memory is ready to output data or not. the valid data ready output is only active during synchronous burst read operations when the burst length is set to continuous. the valid data ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. valid data ready low, v ol , in- dicates that the data is not, or will not be valid. val- id data ready in a high-impedance state indicates that valid data is or will be available. if the memory is configured for synchronous burst read operations with burst length set to continu- ous then the value of valid data ready, will de- pend on the starting address. if the starting address is aligned to a four word boundary then the continuous burst mode will run without activat- ing the valid data ready output. if the starting ad- dress is not aligned to a four word boundary, valid data ready is low at the beginning of the contin- uous burst read to indicate that the memory needs an internal delay to read the content of the four successive words in the array. unless the burst length is set to continuous and synchronous burst read has been selected, valid data ready is high-impedance. it may be tied to other components with the same valid data ready signal to create a unique system ready signal. when the system clock frequency is between 33mhz and 50mhz and the y latency is set to 2, values of b sampled on odd clock cycles, starting from the first read are not considered. designers should use an external pull-up resistor of the correct value to meet the external timing re- quirements for valid data ready rising. refer to figure 20. word organization (word ). the word organi- zation input, word , selects the x16 or x32 bus width on the m58lv064b. the word organization input is not available on the m58lv064a. when word is low, v il , word-wide x16 bus width is selected; data is read and written to dq0- dq15; dq16-dq31 are at high impedance and a1 is the lsb of the address bus. when word is high, v ih , the double-word wide x32 bus width is selected and the data is read and written to on dq0-dq31; a2 is the lsb of the address bus and a1 is dont care. ready/busy (rb ). the ready/busy output, rb , is an open-drain output that can be used to identify if the program/erase controller is currently active. when ready/busy is high impedance, the memo- ry is ready for any read, program or erase opera- tion. ready/busy is low, v ol , during program and erase operations. when the device is busy it will not accept any additional program or erase com- mands except program/erase suspend. when the program/erase controller is idle, or suspended, ready busy can float high through a pull-up resis- tor. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. ready/busy is not low during a reset unless the reset was applied when the program/erase con- troller was active; ready/busy can rise before re- set/power-down rises. program/erase enable (v pp ). the program/ erase enable input, v pp, is used to protect all blocks, preventing program and erase operations from affecting their data. when program/erase enable is low, v il , any pro- gram or erase operation sent to the command in- terface will cause the v pp status bit (bit3) in the status register to be set. when program/erase enable is high, v ih , program and erase operations can be performed on unprotected blocks. pro- gram/erase enable must be kept high during all program, erase, block protect and block unpro- tect operations, otherwise the operation is not guaranteed to succeed and data may become cor- rupt. v dd supply voltage. the supply voltage, v dd , is the core power supply. all internal circuits draw
m58lv064a, m58lv064b 14/65 their current from the v dd pin, including the pro- gram/erase controller. a 0.1 f capacitor should be connected between the supply voltage, v dd , and the ground, v ss , to decouple the current surges from the power sup- ply. the pcb track widths must be sufficient to carry the currents required during all operations of the parts, see table 16, dc characteristics, for maximum current supply requirements. input/output supply voltage (v ddq ). the in- put/output supply voltage, v ddq , is the input/out- put buffer power supply. all input and output pins and voltage references are powered and mea- sured relative to the input/output supply voltage pin, v ddq . the input/output supply voltage, v ddq , must al- ways be equal or less than the v dd supply volt- age, including during power-up. a 0.1 f capacitor should be connected between the input/output supply voltage, v ddq , and the ground, v ssq , to decouple the current surges from the power supply. if v ddq and v dd are con- nected together then only one decoupling capaci- tor is required. ground (v ss ). ground, v ss, is the reference for all core power supply voltages. ground (v ssq ). ground, v ssq, is the reference for input/output voltage measurements. it is es- sential to connect v ss and v ssq to the same ground .
15/65 m58lv064a, m58lv064b bus operations there are 12 bus operations that control the mem- ory. each of these is described in this section, see tables 2 and 3, bus operations, for a summary. the bus operation is selected through the burst configuration register; the bits in this register are described at the end of this section. on power-up or after a hardware reset the mem- ory defaults to asynchronous bus read and asyn- chronous bus write, no other bus operation can be performed until the burst control register has been configured. synchronous read operations and latch con- trolled bus read operations can only be used to read the memory array. the electronic signature, cfi or status register will be read in asynchro- nous mode regardless of the burst control regis- ter settings. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. asynchronous bus operations for asynchronous bus operations refer to table 3 together with the text below. asynchronous bus read. asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, status register, cfi and block protection status) in the command interface. a valid bus operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 12, asynchronous bus read ac waveforms, and table 17, asynchronous bus read ac characteristics, for details of when the output becomes valid. asynchronous latch controlled bus read. asynchronous latch controlled bus read opera- tions read from the memory cells. the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip en- able and address latch low, v il and keeping write enable high, v ih ; the address is latched on the rising edge of address latch. once latched, the address inputs can change. set output en- able low, v il , to read the data on the data inputs/ outputs; see figure 13, asynchronous latch con- trolled bus read ac waveforms and table 18, asynchronous latch controlled bus read ac characteristics for details on when the output be- comes valid. note that, since the latch enable input is transpar- ent when set low, v il , asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding latch enable low, v il throughout the bus operation. asynchronous page read. asynchronous page read operations are used to read from several ad- dresses within the same memory page. each memory page is 4 words or 2 double-words and has the same a3-a22, only a1 and a2 may change. valid bus operations are the same as asynchro- nous bus read operations but with different tim- ings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings ap- ply again. see figure 14, asynchronous page read ac waveforms and table 19, asynchro- nous page read ac characteristics for details on when the outputs become valid. asynchronous bus write. asynchronous bus write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is dont care during bus write operations. a valid asynchronous bus write operation begins by setting the desired address on the address in- puts and setting latch enable low, v il . the ad- dress inputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. the data in- puts/outputs are latched by the command inter- face on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole asyn- chronous bus write operation. see figures 15, and 17, asynchronous write ac waveforms, and tables 20 and 21, asynchronous write and latch controlled write ac characteristics, for details of the timing requirements. asynchronous latch controlled bus write. asynchronous latch controlled bus write opera- tions write to the command interface in order to send commands to the memory or to latch ad- dresses and input data to program. bus write op- erations are asynchronous, the clock, k, is dont care during bus write operations. a valid asynchronous latch controlled bus write operation begins by setting the desired address on the address inputs and pulsing latch enable low, v il . the address inputs are latched by the com- mand interface on the rising edge of latch enable, chip enable or write enable, whichever occurs
m58lv064a, m58lv064b 16/65 first. the data inputs/outputs are latched by the command interface on the rising edge of chip en- able or write enable, whichever occurs first. out- put enable must remain high, v ih , during the whole asynchronous bus write operation. see figures 16 and 18 asynchronous latch controlled write ac waveforms, and tables 20 and 21, asynchronous write and latch controlled write ac characteristics, for details of the timing re- quirements. output disable. the data inputs/outputs are in the high impedance state when the output enable is high. standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high imped- ance state regardless of output enable or write enable. the supply current is reduced to the standby supply current, i dd1 . during program or erase operations the memory will continue to use the program/erase supply current, i dd3 , for program or erase operations un- til the operation completes. automatic low power. if there is no change in the state of the bus for a short period of time during asynchronous bus read operations the memory enters auto low power mode where the internal supply current is reduced to the auto-standby supply current, i dd5 . the data inputs/outputs will still output data if a bus read operation is in progress. automatic low power is only available in asyn- chronous read modes. power-down. the memory is in power-down mode when reset/power-down, rp , is low. the power consumption is reduced to the power-down level, i dd2 , and the outputs are high impedance, independent of chip enable, output enable or write enable. table 2. asynchronous bus operations note: 1. x = dont care v il or v ih . high = v ih or v hh . 2. m15 = 1, bits m15 and m3 are in the burst configuration register. bus operation step e g w rp m3 (2) l a1-a22 dq0-dq31 asynchronous bus read v il v il v ih high 0 x address data output asynchronous latch controlled bus read address latch v il v il v ih high 1 v il address high z read v il v il v ih high 1 v ih x data output asynchronous page read v il v il v ih high 0 x address data output asynchronous bus write v il v ih v il high x v il address data input asynchronous latch controlled bus write address latch v il v ih v il high x v il address data input output disable v il v ih v ih high x x x high z standby v ih x x high x x x high z power-down x x x v il x x x high z
17/65 m58lv064a, m58lv064b synchronous bus operations for synchronous bus operations refer to table 3 together with the text below. synchronous burst read. synchronous burst read operations are used to read from the memo- ry at specific times synchronized to an external ref- erence clock. the burst type, length and latency can be configured. the different configurations for synchronous burst read operations are de- scribed in the burst configuration register sec- tion. a valid synchronous burst read operation begins when the address is set on the address inputs, write enable is high, v ih , and chip enable and latch enable are low, v il , during the active edge of the clock. the address is latched on the first ac- tive clock edge when latch enable is low, or on the rising edge of latch enable, whichever occurs first. the data becomes available for output after the x-latency specified in the burst control regis- ter has expired. the output buffers are activated by setting output enable low, v il . see figure 7 for an example of a synchronous burst read op- eration. the burst address advance input and the y-laten- cy specified in the burst control register deter- mine whether the internal address counter is advanced on the active edge of the clock. when the internal address counter is advanced the data inputs/outputs change to output the value for the next address. in continuous burst mode (burst length bit m2- m0 is set to 111), one burst read operation can access the entire memory sequentially and wrap at the last address. the burst address advance, b , must be kept low, v il , for the appropriate num- ber of clock cycles. if burst address advance, b , is pulled high, v ih , the burst read will be sus- pended. in continuous burst mode, if the starting address is not associated with a page (4 word or 2 double word) boundary the valid data ready, r, output goes low, v il , to indicate that the data will not be ready in time and additional wait-states are re- quired. the valid data ready output timing (bit m8) can be changed in the burst configuration register. when using the x32 bus width certain x-latencies are not valid and must not be used; see table 5, burst configuration register. the synchronous burst read timing diagrams and ac characteristics are described in the ac and dc parameters section. see figures 19, 20 and table 22. synchronous pipelined burst read. synchro- nous burst read operations can be overlapped to avoid or reduce the x-latency. pipelined opera- tions should only be used with burst configuration register bit m9 = 0 (y-latency setting). a valid synchronous pipelined burst read opera- tion occurs during a synchronous burst read op- eration when the new address is set on the address inputs and a low pulse is applied to latch enable. the data for the new address becomes valid after the x-latency specified in the burst con- figuration register has expired. for optimum operation the address should be latched on the correct clock cycle. table 4 gives the clock cycle for each valid x- and y-latency set- ting. only these settings are valid, other settings must not be used. there is always one y-latency period where the data is not valid. if the address is latched later than the clock cycle specified in ta- bles 4 then additional cycles where the data is not valid are inserted. see figure 8 for an example of a synchronous pipelined burst read operation. here the x-latency is 8, the y-latency is 1 and the burst length is 4; the first address is latched on cy- cle 1 while the next address is latched on cycle 6, as shown in table 4. synchronous pipelined burst read operations should only be performed on burst lengths of 4 or 8 with a x16 bus width or a burst length of 4 with a x32 bus width. suspending a pipelined synchronous burst read operation is not recommended. synchronous burst read suspend. during a synchronous burst read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. a valid synchronous burst read operation is sus- pended when both output enable and burst ad- dress advance are high, v ih . the burst address advance going high, v ih , stops the burst counter and the output enable going high, v ih , inhibits the data outputs. the synchronous burst read oper- ation can be resumed by setting output enable low. see figure 7 for an example of a synchro- nous burst read suspend operation.
m58lv064a, m58lv064b 18/65 table 3. synchronous burst read bus operations note: 1. x = don't care, v il or v ih . 2. m15 = 0, bit m15 is in the burst configuration register. 3. t = transition, see m6 in the burst configuration register for details on the active edge of k. table 4. address latch cycle for optimum pipelined synchronous burst read bus operation step e g rp k (3) l b a1-a22 dq0-dq31 synchronous burst read pipelined synchronous burst read address latch v il x v ih t v il x address input read (no address advance) v il v il v ih tx v ih data output read (with address advance) v il v il v ih tx v il data output read suspend v il v ih v ih xx v ih high z read resume (no address advance) v il v il v ih tx v ih data output read resume (with address advance) v il v il v ih tx v il data output read abort v ih x v ih xx x high z x-latency y-latency address latch clock cycle burst length = 4 burst length = 8 81 6 10 91 7 11 12 1 10 14 13 1 11 15 15 2 11 19
19/65 m58lv064a, m58lv064b figure 7. synchronous burst read operation note: in this example the burst configuration register is set with m2-m0 = 001 (burst length = 4 words or double words), m6 = 1 (valid clock edge = rising clock edge), m7 = 0 or 1 (burst type = interleaved or sequential), m9 = 0 (y-latency = 1), m14-m11 = 0011 (x- latency = 8) and m15 = 0 (read select = synchronous burst read), other bits are dont care. figure 8. example synchronous pipelined burst read operation note: in this example the burst configuration register is set with m2-m0 = 001 (burst length = 4 words or double words), m6 = 1 (valid clock edge = rising clock edge), m7 = 0 or 1 (burst type = interleaved or sequential), m9 = 0 (y-latency = 1), m14-m11 = 0011 (x- latency = 8) and m15 = 0 (read select = synchronous burst read), other bits are dont care. ai03454b data inputs/ outputs address inputs l k q1 x+1 x x-1 1 0 q1 q2 b q5 q5 q5 q4 q3 q7 q6 q8 q8 q7 tblkh tbhkh tbhkh tbhkh ai03455 data inputs/ outputs address inputs l e g k q1 b 01234567891011121314 q2 q3 q4 nv r1 r2 r3 r4 nv s1 s2 q1 r1 s1 15 s3 nv= not valid
m58lv064a, m58lv064b 20/65 figure 9. example burst address advance and burst abort operations note: 1. in this example the burst configuration register is set with m2-m0 = 010 (burst length = 8 words), m6 = 1 (valid clock e dge = rising clock edge), m7 = 0 or 1 (burst type = interleaved or sequential), m9 = 1 (y-latency = 2), m14-m11 = 0011 (x-latency = 8) and m15 = 0 (read select = synchronous burst read), other bits are dont care. 2. when the system clock frequency is between 33mhz and 50mhz and the y latency is set to 2, values of b sampled on odd clock cycles, starting from the first read are not considered. ai03457b data inputs/ outputs address inputs l k q1 x+2 x x-2 1 0 q1 q2 b q4 q3 tblkh tbhkh tbhkh tbhkh x+6 x+4 x+12 x+10 x+8 q3 q4 q4
21/65 m58lv064a, m58lv064b burst configuration register the burst configuration register is used to config- ure the type of bus access that the memory will perform. the burst configuration register is set through the command interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into reset/power-down mode. the burst configuration register bits are de- scribed in table 5. they specify the selection of the burst length, burst type, burst x and y laten- cies and the read operation. read select bit (m15). the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to 1, bus read operations are asynchronous; when the read select but is set to 0, bus read operations are synchronous. on reset or power-up the read select bit is set to1 for asynchronous accesses. x-latency bits (m14-m11). the x-latency bits are used during synchronous bus read opera- tions to set the number of clock cycles between the address being latched and the first data be- coming available. for correct operation the x-la- tency bits can only assume the values in table 5, burst configuration register. the x-latency bits should also be selected in conjunction with table 8, burst performance to ensure valid settings. y-latency bit (m9). the y-latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. the y-latency value depends on both the x-latency value and the setting in m9. when the y-latency is 1 the data changes each clock cycle; when the y-latency is 2 the data changes every second clock cycle. see table 5, burst configuration register and table 8, burst performance, for valid combinations of the y-la- tency, the x-latency and the clock frequency. valid data ready bit (m8). the valid data ready bit controls the timing of the valid data ready output pin, r. when the valid data ready bit is 0 the valid data ready output pin is driven low for the active clock edge when invalid data is output on the bus. when the valid data ready bit is 1 the valid data ready output pin is driven low one clock cycle prior to invalid data being output on the bus. burst type bit (m7). the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is 0 the memory outputs from interleaved ad- dresses; when the burst type bit is 1 the memory outputs from sequential addresses. see tables 6 and 7, burst type definition, for the sequence of addresses output from a given starting address in each mode. valid clock edge bit (m6). the valid clock edge bit, m6, is used to configure the active edge of the clock, k, during synchronous burst read opera- tions. when the valid clock edge bit is 0 the fall- ing edge of the clock is the active edge; when the valid clock edge bit is 1 the rising edge of the clock is active. latch enable bit (m3). the latch enable bit is used to select between asynchronous random read and asynchronous latch enable controlled read. when the latch enable bit is set to 0 ran- dom read is selected; when it is set to 1 latch en- able controlled read is selected. to enable these asynchronous read configurations m15 must be set to 1. burst length bit (m2-m0). the burst length bits set the maximum number of words or double- words that can be output during a synchronous burst read operation before the address wraps. table 5, burst configuration register gives the valid combinations of the burst length bits that the memory accepts; tables 6 and 7, burst type def- inition, give the sequence of addresses output from a given starting address for each length. m10, m5 and m4 are reserved for future use.
m58lv064a, m58lv064b 22/65 table 5. burst configuration register address bit mnemonic bit name reset value value description valid bus width 17 m15 read select 1 0 synchronous burst read x16 or x32 1 asynchronous bus read x16 or x32 16 to 13 m14-m11 x-latency xxxx 0010 x-latency = 7, use only with continuous burst length x16 or x32 0011 x-latency = 8 x16 or x32 0100 x-latency = 9 x16 or x32 0101 x-latency = 10, use only with continuous burst length x16 only 0110 x-latency = 11, use only with continuous burst length x16 only 1001 x-latency = 12 x16 only 1010 x-latency = 13 x16 only 1011 x-latency = 13, use only with continuous burst length x16 or x32 1101 x-latency = 15 x16 or x32 others reserved, do not use. 11 m9 y-latency x 0 when x-latency < 13, y-latency = 1 when m14-m11 = 1011 or 1101, y-latency = 2 x16 or x32 1 when x-latency 15 but m14-m11 1011 or 1101, y-latency = 2, when m14-m11 = 1011 or 1101 do not use. x16 or x32 10 m8 valid data ready x 0 r valid low during valid clock edge x16 or x32 1 r valid low one cycle before valid clock edge x16 or x32 9 m7 burst type x 0 interleaved x16 or x32 1 sequential x16 or x32 8m6 valid clock edge x 0 falling clock edge x16 or x32 1 rising clock edge x16 or x32 5m3 latch enable 0 0 random read x16 or x32 1 latch enable controlled read x16 or x32 4 to 2 m2-m0 burst length xxx 100 1 word or double-word x16 or x32 101 2 words or double-words x16 or x32 001 4 words or double-words x16 or x32 010 8 words x16 only 111 continuous x16 or x32 others reserved, do not use.
23/65 m58lv064a, m58lv064b table 6. burst type definition (x16 bus width) note: x = 0 or 1. table 7. burst type definition (x32 bus width) note: x = 0 or 1. burst length starting address (binary) sequential (decimal) interleaved (decimal) a3 a2 a1 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 continuous a a, a+1, a+2... not valid burst length starting address (binary) sequential (decimal) interleaved (decimal) a3 a2 2 x0 0, 1 0, 1 x1 1, 0 1, 0 4 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 8 not valid continuous a a, a+1, a+2... not valid
m58lv064a, m58lv064b 24/65 table 8. burst performance x-latency y-latency bus width clock frequency mode 7 1 x16, x32 33 mhz continuous only 8 continuous, length 9 7 2 continuous only 8 continuous, length 9 10 1 x16 only 50 mhz continuous only 11 12 continuous, length 13 10 2 continuous only 11 12 continuous, length 13 13 2(m9=0) x16, x32 66 mhz continuous only 15 continuous, length
25/65 m58lv064a, m58lv064b command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. the commands are summarized in table 9, commands. refer to table 9 in conjunction with the text descriptions below. after power-up or a reset operation the memory enters read mode. synchronous read operations and latch con- trolled bus read operations can only be used to read the memory array. the electronic signature, cfi or status register will be read in asynchro- nous mode regardless of the burst control regis- ter settings. once the memory returns to read memory array mode the bus will resume the set- ting in the burst configuration register automati- cally. read memory array command. the read mem- ory array command returns the memory to read mode. one bus write cycle is required to issue the read memory array command and return the memory to read mode. once the command is is- sued the memory remains in read mode until an- other command is issued. from read mode bus read commands will access the memory array. while the program/erase controller is executing a program, erase, block protect or blocks unpro- tect operation the memory will not accept the read memory array command until the operation com- pletes. read electronic signature command. the read electronic signature command is used to read the manufacturer code, the device code and the block protection status. one bus write cycle is re- quired to issue the read electronic signature command. once the command is issued subse- quent bus read operations read the manufacturer code, the device code or the block protection status until another command is issued; see table 10, read electronic signature. read query command. the read query com- mand is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations read from the common flash in- terface memory area. see appendix b, tables 29, 30, 31, 32, 33 and 34 for details on the information contained in the common flash interface (cfi) memory area. note that the addresses for the common flash in- terface memory area are a1-a22 for them58lv064a and a2-a22 for the m58lv064b, regardless of the bus width selected. read status register command. the read sta- tus register command is used to read the status register. one bus write cycle is required to issue the read status register command. once the command is issued subsequent bus read opera- tions read the status register until another com- mand is issued. the status register information is present on the output data bus (dq1-dq7) when both chip en- able and output enable are low, v il . see the section on the status register and table 12 for details on the definitions of the status reg- ister bits clear status register command. the clear sta- tus register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write is required to issue the clear status register command. the bits in the status register are sticky and do not automatically return to 0 when a new write to buffer and program, erase, block protect or block unprotect command is issued. if any error occurs then it is essential to clear any error bits in the sta- tus register by issuing the clear status register command before attempting a new program, erase or resume command. block erase command. the block erase com- mand can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the second bus write cycle latches the block address in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read opera- tions read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operation the memory will only accept the read status register command and the program/erase suspend command. all other commands will be ignored. typical erase times are given in table 11. see appendix c, figure 27, block erase flow- chart and pseudo code, for a suggested flowchart on using the block erase command. write to buffer and program command. the write to buffer and program command is used to program the memory array. up to 4 pages of 4 words (or 2 double words) can be loaded into the write buffer and programmed into the memory. the 4 pages are selected by ad- dresses a3 and a4; each page has the same a3- a22.
m58lv064a, m58lv064b 26/65 four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. is- sue the set up command with the selected memory block address where the program op- eration should occur (any address in the block where the values will be programmed can be used). any bus read operations will start to out- put the status register after the 1st cycle. 2. use one bus write operation to write the same block address along with the value n on the data inputs/output, where n+1 is the number of words (x16 bus width) or double words (x32 bus width) to be programmed. 3. use n+1 bus write operations to load the ad- dress and data for each word or double word into the write buffer. see the constraints on the address combinations listed below. the ad- dresses must have the same a5-a22. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the oper- ation without affecting the data in the memory ar- ray. the status register should be cleared before re-issuing the command. the minimum buffer size for a program operation is a 4 word (or 2 double word) page. inside the page the 4 words are selected by addresses a2 and a1. any attempt to program a single word (or double word) inside the page of a previously erased block will result in the programming of the word, however all other words inside the page will be set to ffffh. for any page, only one write to buffer and pro- gram command can be issued inside a previously erased block. any further program operations on that page must be preceded by an erase operation on the respective block. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command or by using the blocks temporary unprotect feature of the reset/ power-down pin, rp . see appendix c, figure 25, write to buffer and program flowchart and pseudo code, for a sug- gested flowchart on using the write to buffer and program command. program/erase suspend command. the pro- gram/erase suspend comm and is used to pause a write to buffer and program or erase operation. the command will only be accepted during a pro- gram or an erase operation. it can be issued at any time during an erase operation but will only be accepted during a write to buffer and program command if the program/erase controller is run- ning. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/ erase controller has paused. after the program/ erase controller has paused, the memory will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing it is possible for the op- eration to complete. once the program/erase controller status bit (bit 7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 11. during program/erase suspend the read memo- ry array, read status register, read electronic signature, read query and program/erase re- sume commands will be accepted by the com- mand interface. additionally, if the suspended operation was erase then the write to buffer and program, and the program suspend commands will also be accepted. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase re- sume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed correctly. see appendix c, figure 26, program suspend & resume flowchart and pseudo code, and figure 28, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command. the pro- gram/erase resume command can be used to re- start the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. once the com- mand is issued subsequent bus read operations read the status register.
27/65 m58lv064a, m58lv064b set burst configuration register command. the set burst configuration register command is used to write a new value to the burst configura- tion control register which defines the burst length, type, x and y latencies, synchronous/ asynchronous read mode and the valid clock edge configuration. two bus write cycles are required to issue the set burst configuration register command. once the command is issued the memory returns to read mode as if a read memory array command had been issued. the value for the burst configuration register is always presented on a2-a17, regardless of the bus width that is selected. m0 is on a2, m1 on a3, etc.; the other address bits are ignored. block protect command. the block protect command is used to protect a block and prevent program or erase operations from changing the data in it. two bus write cycles are required to is- sue the block protect command; the second bus write cycle latches the block address in the inter- nal state machine and starts the program/erase controller. once the command is issued subse- quent bus read operations read the status reg- ister. see the section on the status register for details on the definitions of the status register bits. during the block protect operation the memory will only accept the read status register command. all other commands will be ignored. typical block protection times are given in table 11. the block protection bits are non-volatile, once set they remain set through reset and power- down/power-up. they are cleared by a blocks un- protect command or temporary disabled by raising the reset/power-down pin to v hh and holding it at that level throughout a block erase or write to buffer and program command. blocks unprotect command. the blocks un- protect command is used to unprotect all of the blocks. two bus write cycles are required to issue the blocks unprotect command; the second bus write cycle starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the block unprotect operation the memory will only accept the read status register com- mand. all other commands will be ignored. typical block protection times are given in table 11.
m58lv064a, m58lv064b 28/65 table 9. commands note: x dont care; pa program address; pd program data; ba any address in the block; n+1 number of addresses to program; bcr burst configuration register value. table 10. read electronic signature note: 1. sba is the start base address of each block. 2. dq31-dq16 are available in the m58lv064b only. 3. x32 bus width is available in the m58lv064b only. 4. the address is presented on a22-a2 in x32 mode, and on a22-a1 in x16 mode. command cycles bus write operations 1st 2nd subsequent final addr data addr data addr data addr data read memory array 1 x ffh read electronic signature 1 x 90h read query 1 x 98h read status register 1 x 70h clear status register 1 x 50h block erase 2 x 20h ba d0h write to buffer and program 4 + n ba e8h ba n pa pd x d0h program/erase suspend 1 x b0h program/erase resume 1 x d0h set burst configuration register 2 bcr 60h bcr 03h block protect 2 ba 60h ba 01h blocks unprotect 2 x 60h x d0h code bus width (3) address (4) data (dq31-dq0) (2) manufacturer code x16 000000h 0020h x32 00000020h device code x16 000001h 0015h (m58lv064a) 0014h (m58lv064b) x32 00000014h (m58lv064b) block protection status x16 sba (1) +02h 0000h (block unprotected) 0001h (block protected) x32 00000000h (block unprotected) 00000001h (block protected)
29/65 m58lv064a, m58lv064b table 11. program, erase times and program erase endurance cycles note: (t a = 0 to 70c; v dd = 2.7v to 3.6v; v ddq =1.8v) parameters m58lv064a/b unit min typ typical after 100k w/e cycles max block (1mb) erase 0.75 0.75 5 s chip program 54 54 s program write buffer 192 192 s program suspend latency time 3 10 s erase suspend latency time 10 30 s block protect time 192 s blocks unprotect time 0.75 s program/erase cycles (per block) 100,000 cycles data retention 20 years
m58lv064a, m58lv064b 30/65 status register the status register provides information on the current or previous program, erase, block protect or blocks unprotect operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, blocks unprotect and program/erase re- sume commands. the status register can be read from any address. the status register can only be read using asyn- chronous bus read operations. once the memory returns to read memory array mode the bus will resume the setting in the burst configuration reg- ister automatically. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable pin or by dis-activating (chip enable, v ih ) and then reactivating (chip en- able and output enable, v il ) the device. status register bits 5, 4, 3 and 1 are associated with various error conditions and can only be reset with the clear status register command. the sta- tus register bits are summarized in table 12, sta- tus register bits. refer to table 12 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low, v ol , the program/erase controller is active and all other status register bits are high imped- ance; when the bit is high, v oh , the program/ erase controller is inactive. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, block protect and blocks unprotect operations the program/erase control- ler status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase con- troller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status and block protection status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended and is waiting to be re- sumed. the erase suspend status should only be considered valid when the program/erase con- troller status bit is high (program/erase controller inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is low, v ol , the program/erase controller is active or has com- pleted its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). when the erase status bit is low, v ol , the mem- ory has successfully verified that the block has erased correctly or all blocks have been unprotect- ed successfully. when the erase status bit is high, v oh , the erase operation has failed. de- pending on the cause of the failure other status register bits may also be set to high, v oh . if only the erase status bit (bit 5) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. if the failure is due to an erase or blocks unprotect with v pp low, v ol , then v pp status bit (bit 3) is also set high, v oh . if the failure is due to an erase on a protected block then block protection status bit (bit 1) is also set high, v oh . if the failure is due to a program or erase incorrect command sequence then program status bit (bit 4) is also set high, v oh . once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program or block protect fail- ure. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is low, v ol , the memory has successfully verified that the write buffer has programmed correctly or the block is protected. when the program status bit is high, v oh , the program or block protect operation has
31/65 m58lv064a, m58lv064b failed. depending on the cause of the failure other status register bits may also be set to high, v oh . if only the program status bit (bit 4) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the write buffer has programmed correctly or that the block is protected. if the failure is due to a program or block protect with v pp low, v ol , then v pp status bit (bit 3) is also set high, v oh . if the failure is due to a program on a protected block then block protection status bit (bit 1) is also set high, v oh . if the failure is due to a program or erase incorrect command sequence then erase status bit (bit 5) is also set high, v oh . once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pp status (bit 3). the v pp status bit can be used to identify if a program, erase, block protec- tion or block unprotection operation has been at- tempted when v pp is low, v il . the v pp pin is only sampled at the beginning of a program or erase operation. when the v pp status bit is low, v ol , no program, erase, block protection or block unprotection op- erations have been attempted with v pp low, v il , since the last clear status register command, or hardware reset. when the v pp status bit is high, v oh , a program, erase, block protection or block unprotection operation has been attempted with v pp low, v il . once set high, the v pp status bit can only be reset by a clear status register command or a hard- ware reset. if set high it should be reset before a new program, erase, block protection or block unprotection command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended and is waiting to be re- sumed. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase con- troller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is low, v ol , the program/erase controller is active or has completed its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a protected block. when the block protection status bit is low, v ol , no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is high, v oh , a program (program status bit 4 set high) or erase (erase status bit 5 set high) operation has been attempted on a protected block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value should be masked.
m58lv064a, m58lv064b 32/65 table 12. status register bits note: 1. for program operations during erase suspend bit 6 is 1, otherwise bit 6 is 0. operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 rb program/erase controller active 0 hi-z v ol write buffer not ready 0 hi-z v ol write buffer ready 1 x (1) 0 0 0 0 0 hi-z program suspended 1 x (1) 0 0 0 1 0 hi-z program/block protect completed successfully 1 x (1) 0 0 0 0 0 hi-z program/block protect failure due to incorrect command sequence 1 x (1) 1 1 0 0 0 hi-z program/block protect failure due to v pp error 1 x (1) 0 1 1 0 0 hi-z program failure due to block protection 1 x (1) 0 1 0 0 1 hi-z program/block protect failure due cell failure or unerased cell 1 x (1) 0 1 0 0 0 hi-z erase suspended 1 1 0 0 0 0 0 hi-z erase/blocks unprotect completed successfully 1 0 0 0 0 0 0 hi-z erase/blocks unprotect failure due to incorrect command sequence 1 x 1 1 0 0 0 hi-z erase/block unprotect failure due to v pp error 1 0 1 0 1 0 0 hi-z erase failure due to block protection 1 0 1 0 0 0 1 hi-z erase/blocks unprotect failure due to failed cell(s) in block 1 0 1 0 0 0 0 hi-z
33/65 m58lv064a, m58lv064b maximum rating stressing the device above the ratings listed in ta- ble 13, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 13. absolute maximum ratings note: 1. cumulative time at a high voltage level of 10v should not exceed 80 hours on rp pin. symbol parameter value unit min max t bias temperature under bias C40 125 c t stg storage temperature C55 150 c t lead maximum tlead temperature during soldering t.b.a. c v io input or output voltage C0.6 v ddq +0.6 v v dd , v ddq supply voltage C0.6 5.0 v v hh rp hardware block unprotect voltage C0.6 10 (1) v
m58lv064a, m58lv064b 34/65 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 14, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 14. operating and ac measurement conditions figure 10. ac measurement input output waveform figure 11. ac measurement load circuit table 15. capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter m58lv064 units min max supply voltage (v dd ) m58lv064 3.0 3.6 v input/output supply voltage (v ddq ) 1.8 v dd v ambient temperature (t a ) grade 1 0 70 c grade 6 C40 85 c load capacitance (c l ) 30 pf clock rise and fall times 3 ns input rise and fall times 4 ns input pulses voltages 0 to v ddq v input and output timing ref. voltages 0.5 v ddq v ai00610 v ddq 0v 0.5 v ddq ai03459 1.3v dq s c l c l includes jig capacitance 3.3k 1n914 device under test 0.1f v dd v ddq 0.1f symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
35/65 m58lv064a, m58lv064b table 16. dc characteristics note: 1. biasing rp pin to v hh is allowed for a maximum cumulative period of 80 hours. symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd supply current (random read) e = v il , g = v ih , f add = 6mhz 30 ma i ddb supply current (burst read) e = v il , g = v ih , f clock = 50mhz 50 ma i dd1 supply current (standby) e = v ih , rp = v ih 40 a i dd5 supply current (auto low-power) e = v il , rp = v ih 2ma i dd2 supply current (reset/power-down) rp = v il 1 a i dd3 supply current (program or erase, set block protection, unprotection) program or erase operation in progress 50 ma i dd4 supply current (erase/program suspend) e = v ih 50 ma v il input low voltage C0.5 0.8 v v ih input high voltage v ddq C0.8 v ddq + 0.5 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = C100a v ddq C0.1 v v hh (1) rp hardware block unprotect voltage block erase in progress, write to buffer and program 8.5 9.5 v i hh rp hardware block unprotect current rp = v hh 1 a v lko v dd supply voltage (erase and program lockout) 2.2 v
m58lv064a, m58lv064b 36/65 figure 12. asynchronous bus read ac waveforms note: asynchronous read (m15 = 1), random read (m3 = 0) table 17. asynchronous bus read ac characteristics. symbol parameter test condition m58lv064 unit 150 t avav address valid to address valid e = v il , g = v il min 150 ns t av qv address valid to output valid e = v il , g = v il max 150 ns t elqx chip enable low to output transition g = v il min 0 ns t elqv chip enable low to output valid g = v il max 150 ns t glqx output enable low to output transition e = v il min 0 ns t glqv output enable low to output valid e = v il max 30 ns t ehqx chip enable high to output transition g = v il min 0 ns t ghqx output enable high to output transition e = v il min 0 ns t axqx address transition to output transition e = v il , g = v il min 0 ns t ehqz chip enable high to output hi-z g = v il max 10 ns t ghqz output enable high to output hi-z e = v il max 10 ns ai03250b e g a1-a22 dq0-dqx valid taxqx telqx tavqv tglqv tehqz tghqx output tavav tehqx tghqz tglqx telqv
37/65 m58lv064a, m58lv064b figure 13. asynchronous latch controlled bus read ac waveforms note: asynchronous read (m15 = 1), latch enable controlled (m3 = 1) table 18. asynchronous latch controlled bus read ac characteristics note: for other timings see table 17, asynchronous bus read characteristics. symbol parameter test condition m58lv064 unit 150 t avll address valid to latch enable low e = v il min 0 ns t av lh address valid to latch enable high e = v il min 10 ns t lhll latch enable high to latch enable low min 10 ns t lllh latch enable low to latch enable high e = v il min 10 ns t elll chip enable low to latch enable low min 0 ns t ellh chip enable low to latch enable high min 10 ns t llqx latch enable low to output transition e = v il , g = v il min 0 ns t llqv latch enable low to output valid e = v il , g = v il min 150 ns t lhax latch enable high to address transition e = v il min 10 ns t glqx output enable low to output transition e = v il min 0 ns t glqv output enable low to output valid e = v il max 20 ns t ehlx chip enable high to latch enable transition min 0 ns ai03251b l e g a1-a22 dq0-dqx valid tehlx tlhll tlhax tavll telll tlllh tehqx tghqz tllqv tglqv output tavlh tellh tghqx tllqx tehqz tglqx
m58lv064a, m58lv064b 38/65 figure 14. asynchronous page read ac waveforms note: asynchronous read (m15 = 1), random (m3 = 0) table 19. asynchronous page read ac characteristics note: for other timings see table 17, asynchronous bus read characteristics. symbol parameter test condition m58lv064 unit 150 t axqx1 address transition to output transition e = v il , g = v il min 6 ns t avqv1 address valid to output valid e = v il , g = v il max 25 ns ai03451b e g a3-a22 dq0-dqx valid taxqx telqx tavqv tglqv tehqx tghqz output output a1-a2 taxqx1 valid valid tghqx tehqz telqv tglqx tavqv1
39/65 m58lv064a, m58lv064b figure 15. asynchronous write ac waveform, write enable controlled figure 16. asynchronous latch controlled write ac waveform, write enable controlled ai03694c dq0-dq15 rb w a1-a22 e g input valid twheh tavwh twlwh telwl v pp twhax twhwl twhdx tdvwh tvphwh twhgl tghwl twhbl l ai03693c dq0-dq15 rb w a1-a22 e g input valid twheh tavlh twlwh telll v pp tlhax twhwl twhdx tdvwh tvphwh twhgl tghwl twhbl tlllh telwl l tlhgl twhax tlhwh tavwh twllh
m58lv064a, m58lv064b 40/65 table 20. asynchronous write and latch controlled write ac characteristics, write enable controlled. symbol parameter test condition m58lv064 unit 150 t avlh address valid to latch enable high min 10 ns t av wh address valid to write enable high e = v il min 50 ns t dvwh data input valid to write enable high e = v il min 50 ns t elwl chip enable low to write enable low min 0 ns t elll chip enable low to latch enable low min 0 ns t lhax latch enable high to address transition min 3 ns t lhgl latch enable high to output enable low min 35 ns t lhwh latch enable high to write enable high min 0 ns t lllh latch enable low to latch enable high min 10 ns t llwh latch enable low to write enable high min 50 ns t vphwh program/erase enable high to write enable high min 0 ns t whax write enable high to address transition e = v il min 10 ns t whbl write enable high to ready/busy low max 90 ns t whdx write enable high to input transition e = v il min 10 ns t wheh write enable high to chip enable high min 0 ns t ghwl output enable high to write enable low min 20 ns t whgl write enable high to output enable low min 35 ns t whwl write enable high to write enable low min 30 ns t wlwh write enable low to write enable high e = v il min 70 ns t wllh write enable low to latch enable high e = v il min 10 ns
41/65 m58lv064a, m58lv064b figure 17. asynchronous write ac waveforms, chip enable controlled figure 18. asynchronous latch controlled write ac waveforms, chip enable controlled ai03429c dq0-dq15 rb e a1-a22 w g input valid tehwh taveh teleh twlel v pp tehax tehel tehdx tdveh tvpheh tehgl tghel tehbl l ai03430c dq0-dq15 rb e a1-a22 w g input valid tehwh tavlh teleh twlll v pp tlhax tehel tehdx tdveh tvpheh tehgl tghel tehbl tlllh twlel l tehax taveh tlhgl tlheh tellh
m58lv064a, m58lv064b 42/65 table 21. asynchronous write and latch controlled write ac characteristics, chip enable controlled symbol parameter test condition m58lv064 unit 150 t avl h address valid to latch enable high min 10 ns t av eh address valid to chip enable high w = v il min 50 ns t dveh data input valid to chip enable high w = v il min 50 ns t wlel write enable low to chip enable low min 0 ns t wlll write enable low to latch enable low min 0 ns t lhax latch enable high to address transition min 3 ns t lhgl latch enable high to output enable low min 35 ns t lheh latch enable high to chip enable high min 0 ns t lllh latch enable low to latch enable high min 10 ns t lleh latch enable low to chip enable high min 50 ns t vpheh program/erase enable high to chip enable high min 0 ns t ehax chip enable high to address transition w = v il min 10 ns t ehbl chip enable high to ready/busy low max 90 ns t ehdx chip enable high to input transition w = v il min 10 ns t ehwh chip enable high to write enable high min 0 ns t ghel output enable high to chip enable low min 20 ns t ehgl chip enable high to output enable low min 35 ns t ehel chip enable high to chip enable low min 30 ns t eleh chip enable low to chip enable high w = v il min 70 ns t ellh chip enable low to latch enable high w = v il min 10 ns
43/65 m58lv064a, m58lv064b figure 19. synchronous burst read ac waveform note: valid clock edge = rising (m6 = 1) ai03256b dq0-dqx a1-a22 l e g k valid tkhax tqvkh x+2y x+y x x-1 2 1 0 tkhll tllkh telkh tavkh tehqz tghqz tglkh q1 q2 q3 tkhqx x+2y+1 tblkh tbhkh tkhbh tkhbl x+2y+2 b tkhqv tlllh tlhax tavlh tellh tghqx tehqx
m58lv064a, m58lv064b 44/65 figure 20. synchronous burst read - continuous - valid data ready output note: 1. valid data ready = valid low during valid clock edge (m8 = 0) 2. v= valid output, nv= not valid output. 3. r is an open drain output . depending on the valid data ready pin capacitance load an external pull up resistor must be chosen according to the system clock period. 4. when the system clock frequency is between 33mhz and 50mhz and the y latency is set to 2, values of b sampled on odd clock cycles, starting from the first read are not considered. ai03696 k output (2) v v nv nv v v trlkh r v (3)
45/65 m58lv064a, m58lv064b table 22. synchronous burst read ac characteristics note: for other timings see table 17, asynchronous bus read characteristics. symbol parameter test condition m58lv064 unit 150 t avk h address valid to active clock edge e = v il min 10 ns t avlh address valid to latch enable high e = v il min 10 ns t bhkh burst address advance high to active clock edge e = v il , g = v il , l = v ih min 10 ns t blkh burst address advance low to active clock edge e = v il , g = v il , l = v ih min 10 ns t elkh chip enable low to active clock edge e = v il min 10 ns t ellh chip enable low to latch enable high e = v il min 10 ns t glkh output enable low to valid clock edge e = v il , l = v ih min 20 ns t khax valid clock edge to address transition e = v il min 10 ns t khll valid clock edge to latch enable low e = v il min 0 ns t khlh valid clock edge to latch enable high e = v il min 0 ns t khqx valid clock edge to output transition e = v il , g = v il , l = v ih min 3 ns t llkh latch enable low to valid clock edge e = v il min 10 ns t lllh latch enable low to latch enable high e = v il min 10 ns t khqv valid clock edge to output valid e = v il , g = v il , l = v ih max 20 ns t qvkh output valid to active clock edge e = v il , g = v il , l = v ih min 5 ns t rlkh valid data ready low to valid clock edge e = v il , g = v il , l = v ih min 5 ns t khbl active clock edge to burst address advance low e = v il , g = v il , l = v ih min 0 ns t khbh active clock edge to burst address advance high e = v il , g = v il , l = v ih min 0 ns
m58lv064a, m58lv064b 46/65 figure 21. reset, power-down and power-up ac waveform note: write enable (w ) and output enable (g ) cannot be low together. table 23. reset, power-down and power-up ac characteristics symbol parameter m58lv064 unit 150 t phqv reset/power-down high to data valid min 10 s t rhwl t rhel t rhgl ready/busy high to write enable low, chip enable low, output enable low (program/erase controller active) min 10 s t plph reset/power-down low to reset/power-down high min 100 ns t plrh reset/power-down low to ready high max 30 s t vdhph supply voltages high to reset/power-down high min 1 s ai03453b rb w rp e, g trhwl trhel trhgl vdd, vddq tvdhph tplph tplrh power-up and reset reset during program or erase dq0-dq15 tphqv
47/65 m58lv064a, m58lv064b package mechanical figure 22. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline note: drawing is not to scale. table 24. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 13.90 14.10 0.5472 0.5551 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 0 5 0 5 n56 56 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1
m58lv064a, m58lv064b 48/65 figure 23. tbga64 - 10x13mm, 8 x 8 ball array 1mm pitch, package outline note: drawing is not to scale. table 25. tbga64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.850 0.0335 b 0.400 0.500 0.0157 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 C C 0.2756 C C ddd 0.100 0.0039 e 1.000 C C 0.0394 C C e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 C C 0.2756 C C fd 1.500 C C 0.0591 C C fe 3.000 C C 0.1181 C C sd 0.500 C C 0.0197 C C se 0.500 C C 0.0197 C C e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
49/65 m58lv064a, m58lv064b figure 24. tbga80 - 10x13mm, 8 x 10 ball array, 1mm pitch, package outline note: drawing is not to scale. table 26. tbga80 - 10x13mm, 8 x 10 ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.850 0.0335 b 0.400 0.500 0.0157 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 C C 0.2756 C C ddd 0.100 0.0039 e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 9.000 C C 0.3543 C C e 1.000 C C 0.0394 C C fd 1.500 C C 0.0591 C C fe 2.000 C C 0.0787 C C sd 0.500 C C 0.0197 C C se 0.500 C C 0.0197 C C e1 e d1 d eb a2 a1 a bga-z27 ddd fd fe sd se e ball "a1"
m58lv064a, m58lv064b 50/65 part numbering table 27. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m58lv064a 150 n 1 t device type m58 architecture l = multi-bit cell, burst mode, page mode operating voltage v = v dd = 3.0v to 3.6v; v ddq = 1.8 to v dd device function 064a = 64 mbit (x16), uniform block 064b = 64 mbit (x16/x32), uniform block speed 150 = 150 ns package n = tsop56: 14 x 20 mm (m58lv064a) za = tbga64: 10 x 13mm, 1mm pitch (m58lv064a) za = tbga80: 10 x 13mm, 1mm pitch (m58lv064b) temperature range 1 = 0 to 70 c 6 = C40 to 85 c option t = tape & reel packing
51/65 m58lv064a, m58lv064b appendix a. block address table table 28. block addresses block number address range (x16 bus width) address range (x32 bus width) 64 3f0000h-3fffffh 1f8000h-1fffffh 63 3e0000h-3effffh 1f0000h-1f7fffh 62 3d0000h-3dffffh 1e8000h-1effffh 61 3c0000h-3cffffh 1e0000h-1e7fffh 60 3b0000h-3bffffh 1d8000h-1dffffh 59 3a0000h-3affffh 1d0000h-1d7fffh 58 390000h-39ffffh 1c8000h-1cffffh 57 380000h-38ffffh 1c0000h-1c7fffh 56 370000h-37ffffh 1b8000h-1bffffh 55 360000h-36ffffh 1b0000h-1b7fffh 54 350000h-35ffffh 1a8000h-1affffh 53 340000h-34ffffh 1a0000h-1a7fffh 52 330000h-33ffffh 198000h-19ffffh 51 320000h-32ffffh 190000h-197fffh 50 310000h-31ffffh 188000h-18ffffh 49 300000h-30ffffh 180000h-187fffh 48 2f0000h-2fffffh 178000h-17ffffh 47 2e0000h-2effffh 170000h-177fffh 46 2d0000h-2dffffh 168000h-16ffffh 45 2c0000h-2cffffh 160000h-167fffh 44 2b0000h-2bffffh 158000h-15ffffh 43 2a0000h-2affffh 150000h-157fffh 42 290000h-29ffffh 148000h-14ffffh 41 280000h-28ffffh 140000h-147fffh 40 270000h-27ffffh 138000h-13ffffh 39 260000h-26ffffh 130000h-137fffh 38 250000h-25ffffh 128000h-12ffffh 37 240000h-24ffffh 120000h-127fffh 36 230000h-23ffffh 118000h-11ffffh 35 220000h-22ffffh 110000h-117fffh 34 210000h-21ffffh 108000h-10ffffh 33 200000h-20ffffh 100000h-107fffh 32 1f0000h-1fffffh 0f8000h-0fffffh 31 1e0000h-1effffh 0f0000h-0f7fffh 30 1d0000h-1dffffh 0e8000h-0effffh 29 1c0000h-1cffffh 0e0000h-0e7fffh 28 1b0000h-1bffffh 0d8000h-0dffffh 27 1a0000h-1affffh 0d0000h-0d7fffh 26 190000h-19ffffh 0c8000h-0cffffh 25 180000h-18ffffh 0c0000h-0c7fffh 24 170000h-17ffffh 0b8000h-0bffffh 23 160000h-16ffffh 0b0000h-0b7fffh 22 150000h-15ffffh 0a8000h-0affffh 21 140000h-14ffffh 0a0000h-0a7fffh 20 130000h-13ffffh 098000h-09ffffh 19 120000h-12ffffh 090000h-097fffh 18 110000h-11ffffh 088000h-08ffffh 17 100000h-10ffffh 080000h-087fffh 16 0f0000h-0fffffh 078000h-07ffffh 15 0e0000h-0effffh 070000h-077fffh 14 0d0000h-0dffffh 068000h-06ffffh 13 0c0000h-0cffffh 060000h-067fffh 12 0b0000h-0bffffh 058000h-05ffffh 11 0a0000h-0affffh 050000h-057fffh 10 090000h-09ffffh 048000h-04ffffh 9 080000h-08ffffh 040000h-047fffh 8 070000h-07ffffh 038000h-03ffffh 7 060000h-06ffffh 030000h-037fffh 6 050000h-05ffffh 028000h-02ffffh 5 040000h-04ffffh 020000h-027fffh 4 030000h-03ffffh 018000h-01ffffh 3 020000h-02ffffh 010000h-017fffh 2 010000h-01ffffh 008000h-00ffffh 1 000000h-00ffffh 000000h-007fffh block number address range (x16 bus width) address range (x32 bus width)
m58lv064a, m58lv064b 52/65 appendix b. common flash interface - cfi the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 29, 30, 31, 32, 33 and 34 show the addresses used to re- trieve the data. when the m58lv064b is used in x16 mode , a1 is the least significant address. toggling a1 will not change the cfi information available on the dq15-dq0 outputs. to read the cfi, in the m58lv064a and m58lv064b devices, in x16 mode, addresses a23-a1 are used; for the x32 mode of the m58lv064b device only addresses a23-a2 are used. to read the cfi, in the m58lv064b device, in x16 mode, the address offsets shown must be multiplied by two in hexadecimal. table 29. query structure overview note: 1. offset 15h defines p which points to the primary algorithm extended query address table. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. sba is the start base address for each block. offset sub-section name description 00h manufacturer code 01h device code 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash memory layout p(h) (1) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) (sba+02)h block status register block-related information
53/65 m58lv064a, m58lv064b table 30. cfi - query address and data output note: 1. the x8 or byte address mode is not available. 2. with the x16 bus width, the value of the address location of the cfi query is independent of a1 pad (m58lv064b). 3. query data are always presented on dq7-dq0. dq31-dq8 are set to '0'. 4. for m58lv064b, a1 = dont care. 5. offset 19h defines a which points to the alternate algorithm extended query address table. 6. dq31-dq16 are available in the m58lv064b only. they are in the high-impedance state when the device operates in x16 mode. address (4) a22-a1 (m58lv064a) a22-a2 (m58lv064b) data instruction dq31-dq16 (6) dq15-dq0 10h 0000 0051h 0051h; "q" query ascii string 0052h; "r" 0059h; "y" 11h 0000 0052h 12h 0000 0059h 13h 0000 0001h primary vendor: command set and control interface id code 14h 0000 0000h 15h 0000 0031h primary algorithm extended query address table: p(h) 16h 0000 0000h 17h 0000 0000h alternate vendor: command set and control interface id code 18h 0000 0000h 19h 0000 0000h alternate algorithm extended query address table 1ah (5) 0000 0000h
m58lv064a, m58lv064b 54/65 table 31. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volts and bit3 to bit0 in mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volts while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. 4. for m58lv064b, a1 = dont care. 5. dq31-dq16 are available in the m58lv064b only. they are in the high-impedance state when the device operates in x16 mode. address (4) a22-a1 (m58lv064a) a22-a2 (m58lv064b) dq31-dq16 (5) dq15-dq0 description 1bh 0000h 0030h (1) v dd min, 3.0v m58lv064 1ch 0000h 0036h (1) v dd max, 3.6v 1dh 0000h 0000h (2) v pp min C not available 1eh 0000h 0000h (2) v pp max C not available 1fh 0000h 0007h 2 n s typical time-out for word program, dword program C not available 20h 0000h 0007h 2 n s typical time-out for max buffer write 21h 0000h 000ah 2 n ms, typical time-out for erase block 22h 0000h 0000h (3) 2 n ms, typical time-out for chip erase C not available 23h 0000h 0004h 2 n x typical for word program time-out max C (dword not available) 24h 0000h 0004h 2 n x typical for buffer write time-out max 25h 0000h 0004h 2 n x typical for individual block erase time-out maximum 26h 0000h 0000h (3) 2 n x typical for chip erase max time-out C not available
55/65 m58lv064a, m58lv064b table 32. device geometry definition note: 1. for m58lv064b, a1 = dont care. n/a = not applicable 2. dq31-dq16 are available in the m58lv064b only. they are in the high-impedance state when the device operates in x16 mode. table 33. block status register note: 1. ba specifies the block address location, a22-a17. address (1) a22-a1 (m58lv064a) a22-a2 (m58lv064b) dq31-dq16 (2) dq15-dq0 description 27h 0000h 0017h 2 n number of bytes memory size 28h n/a 0001h device interface m58lv064a 0000h 0004h device interface m58lv064b 29h 0000h 0000h 2ah 0000h 0005h maximum number of bytes in write buffer, 2 n 2bh 0000h 0000h 2ch 0000h 0001h bit7-0 = number of erase block regions in device 2dh 0000h 003fh number (n-1) of erase blocks of identical size; n=64 2eh 0000h 0000h 2fh 0000h 0000h erase block region information x 256 bytes per erase block (128k bytes) 30h 0000h 0002h address a22-a1 (m58lv064a) a22-a2 (m58lv064b) data selected block information (ba+2)h (1) bit0 0 block unprotected 1 block protected bit7-1 0 reserved for future features
m58lv064a, m58lv064b 56/65 table 34. extended query information note: 1. dq31-dq16 are available in the m58lv064b only. they are in the high-impedance state when the device operates in x16 mode . address offset address a22-a1 (m58lv064a) a22-a2 (m58lv064b) dq31-dq16 (1) dq15-dq0 description (p)h 31h 0000h 0050h 0050h; p query ascii string - extended table 0052h; r 0059h; y (p+1)h 32h 0000h 0052h (p+2)h 33h 0000h 0049h (p+3)h 34h 0000h 0031h major version number (p+4)h 35h 0000h 0031h minor version number (p+5)h 36h 0000h 008eh optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, protect/unprotect supported (1=yes) bit4, queue erase supported (0=no) bit5, instant individual block locking supported (0=no) bit6, protection bits supported (0=no) bit7, page read supported (1=yes) bit8, synchronous read supported (1=yes) bit 31-9 reserved for future use (p+6)h 37h 0000h 0001h (p+7)h 38h 0000h 0000h (p+8)h 39h 0000h 0000h (p+9)h 3ah 0000h 0001h supported functions after suspend: program allowed after erase suspend (1=yes) (refer to commands for other allowed functions) bit 7-1 reserved for future use (p+a)h 3bh 0000h 0001h block status register bit 0 block protect bit status active (1=yes) bits 1-15 are reserved (p+b)h (p+c)h 3ch 0000h 0033h v dd optimum program/erase voltage conditions (p+d)h 3dh 0000h 0033h v pp optimum program/erase voltage conditions (p+e)h 3eh 0000h 00ffh not available (p+f)h 3fh 0000h 00ffh not available (p+10)h 40h 0000h 00ffh not available (p+11)h 41h 0000h 00ffh not available (p+12)h 42h 0000h 00ffh not available (p+13)h 43h 0000h 0003h page read: 2 n bytes (n = bits 0-7) (p+14)h 44h 0000h 0004h synchronous mode configuration fields (p+15)h 45h 0000h 0000h n where 2 n+1 is the number of words/double-words for the burst length (= 2) (p+16)h 46h 0000h 0001h n where 2 n+1 is the number of words/double-words for the burst length (= 4) (p+17)h 47h 0000h 0002h n where 2 n+1 is the number of words/double-words for the burst length (= 8) (x16 mode only) (p+18)h 48h 0000h 0007h burst continuous
57/65 m58lv064a, m58lv064b appendix c. flow charts figure 25. write to buffer and program flowchart and pseudo code write to buffer e8h command, block address ai03635 start write buffer data, start address yes x = n end no write n (1) , block address x = 0 write next buffer data, next program address (2) x = x + 1 program buffer to flash confirm d0h read status register no b7 = 1 yes full status register check (3) note 1: n+1 is number of words or double words to be programmed note 2: next program address must have same a5-a22. note 3: a full status register check must be done to check the program operation's success.
m58lv064a, m58lv064b 58/65 figure 26. program suspend & resume flowchart and pseudo code write 70h ai00612 read status register yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b2 = 0, program completed read memory array instruction: C write ffh C one or more data reads from other blocks write d0h program erase resume command: C write d0h to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
59/65 m58lv064a, m58lv064b figure 27. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clear status register command) before further program or eras e oper- ations. write 20h ai00613c start write d0h to block address read status register yes no b7 = 1 yes no b3 = 0 yes b4, b5 = 1,1 v pp invalid error (1) command sequence error erase command: C write 20h C write d0h to block address (a12-a17) (memory enters read status register after the erase command) do: C read status register C if program/erase suspend command given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1,1 command sequence error: C error handler no no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: C error handler
m58lv064a, m58lv064b 60/65 figure 28. erase suspend & resume flowchart and pseudo code write 70h ai00615 read status register yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b6 = 0, erase completed read memory array command: C write ffh C one o more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: C write d0h to resume the erase operation C if the program operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
61/65 m58lv064a, m58lv064b figure 29. command interface and program erase controller flowchart (a) ai03618 read signature yes no 90h read status yes 70h no clear status yes 50h no program buffer load yes e8h no erase set-up yes 20h (1) no erase command error yes ffh wait for command write read array yes d0h no a b no c cfi query yes 98h no d0h yes no program command error note 1. the erase command (20h) can only be issued if the flash is not already in erase suspend.
m58lv064a, m58lv064b 62/65 figure 30. command interface and program erase controller flowchart (b) read status yes no 70h b erase yes ready ? no a b0h no read status yes ready ? no erase suspend yes d0h read array yes erase suspended read status (read status) yes (erase resume) no read status 90h no read signature yes 98h no cfi query yes e8h no program buffer load yes c ai03619 program/erase controller status bit in the status register read status d0h yes no no program command error wait for command write ffh yes read array no
63/65 m58lv064a, m58lv064b figure 31. command interface and program erase controller flowchart (c) read status yes no 70h b program yes ready ? no c b0h no read status yes ready ? no program suspend yes d0h read array yes program suspended read status (read status) yes no (program resume) no read status 90h no read signature yes 98h no cfi query yes ai00618 program/erase controller status bit in the status register read status read array yes no ffh wait for command write
m58lv064a, m58lv064b 64/65 revision history table 35. document revision history date version revision details september 1999 -01 first issue. june 2000 -02 corrections. 02-mar-01 -03 major rewrite and restructure. 26-mar-01 -04 corrections in cfi tables, tbga80 and tbga64 package mechanical dimensions updated. 06-apr-01 -05 correction in asynchronous bus write. 15-may-01 -06 120ns speed class added, corrections figures 7 , 8 and 9. 05-jun-01 -07 corrections to figures 15,16,17 and 18. 10-dec-2001 -08 m58lv064 part number added for 3.0 to 3.6 voltage range, 120ns speed class removed, corrections to: program/erase enable signal description, read and clear status register commands, set burst configuration register command and burst configuration register tables, table 10, read electronic signature, descriptions of status register bits 7, 5, 4, 3 and 1, table 12 status register bits, asynchronous read ac characteristics timing t glqv , cfi tables and flowchart figures 25 and 27. corrections to figures 15, 16, 17, 18 and 21, and tables 20, 21 and 23. 08-jul-2002 -09 part numbers m58lw064a and m58lw064b removed from datasheet, parameter t phqv changed in table 23. 16-dec-2002 9.1 version number format modified (major.minor). revision history moved to end of document. m58lv064a and m58lv064b device codes changed. table 10, read electronic signature, clarified. data retention information added to table 11, program, erase times and program erase endurance cycles. cfi information (tables 30, 31, 32 and 34) clarified.
65/65 m58lv064a, m58lv064b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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